Fundamental Analog Circuits Research
(Thrust leader: Pavan Hanumolu, U. of Illinois Urbana-Champaign)
The research in this thrust focuses on cross-cutting areas in analog and mixed-signal circuits, which impact all TxACE application areas (Energy Efficiency, Public Safety, Security, and Health Care). The research includes the design of various analog-to-digital converters, communication links, I/O circuits, noise reduction techniques, temperature sensors, new amplifier topologies suitable for use in nano-scale CMOS, development of CAD tools for AI-assisted design and layout generation, and testing of integrated circuits.
Figure 5. (Top left) CT ΔΣ Modulator (N. Maghari, University of Florida). (Top middle left) Low jitter ring PLL (P. Hanumolu, University of Illinois Urbana-Champaign). (Top middle right) 1024 QAM transmitter (H. Wang, National Taiwan University). (Top right) Subthreshold voltage reference (D. Sylvester, University of Michigan). (Bottom left) Reservoir computer with output ANN layer (A. Sanyal, Arizona State University), (Bottom middle) CNN for PA design (M. Chen, University of Southern California), (Bottom middle) ANN MOS transistor model (R. Rohrer, Carnegie Mellon University).
Fundamental Analog Thrust
| Category | Accomplishment |
|---|---|
| Fundamental Analog (Circuits) | A type-III supply-regulated phase-locked loop (PLL) showcases the potential of ring oscillators for ultra-low noise applications. It utilizes a high-gain sampling phase detector to suppress in-band phase noise, while a low-noise multiphase oscillator reduces out-of-band noise. Fabricated in a 16-nm FinFET process, the prototype PLL operates over a wide frequency range of 7 to 14 GHz, achieving a low integrated jitter of 70 fs RMS and exceptional supply noise rejection exceeding 30dB. (3160.017, P. Hanumolu, University of Illinois, Urbana-Champaign) |
| Fundamental Analog (Circuits) | A nanowatt subthreshold voltage reference minimizes temperature-induced current variation through a clock reference for adaptive duty-cycled operation and offers output voltage programmability via an integrated programmable DC-DC converter. Fabricated in a 0.18-μm CMOS process, it achieves a temperature coefficient of 176ppm/°C while consuming 4.6nW, reduces current variation to 2.75%/°C (a 400× improvement), and features 64-step output voltage programmability with 1.2-mV resolution. (2810.063, D. Sylvester, University of Michigan) |
| Fundamental Analog (CAD) | A data-driven analog circuit synthesizer with automatic topology selection and sizing is demonstrated. An adaptive topology dataset is utilized, which can later be enhanced with synthetic data generated using variational autoencoders (VAE), a generative machine learning technique. This improves the predictive capabilities. Experiments involving over 360 OpAmp topologies and over 540K data points demonstrate the capability to generate designs within minutes while achieving quality comparable to that of experienced designers. (3160.007, D. Pan, University of Texas, Austin) |
