Fundamental Analog Circuits Research

(Thrust leader: Pavan Hanumolu, U. of Illinois Urbana-Champaign)

The research in this thrust focuses on cross-cutting areas in analog and mixed-signal circuits, which impact all TxACE application areas (Energy Efficiency, Public Safety, Security, and Health Care). The research includes the design of various analog-to-digital converters, communication links, I/O circuits, noise reduction techniques, temperature sensors, new amplifier topologies suitable for use in nano-scale CMOS, the development of CAD tools for AI-assisted design and layout generation, and the testing of integrated circuits.

Figure 5. (Top left) Noise-shaping SAR ADC (M. Flynn, University of Michigan). (Top middle left) Direct digital transmitter (M. Chen, University of Southern California). (Top middle right) Time-based ADC (S. Pallermo, Texas A&M University). (Top right) Ring-based PLL (P. Hanumolu, University of Illinois Urbana-Champaign). (Bottom left) 3D-HI phased array (B. Floyd, North Carolina State University), (Bottom middle) LLM analog optimizer (P. Li, University of California, Santa Barbara), (Bottom right) Multi-agent Q-learning framework (D. Pan, University of Texas, Austin).

Fundamental Analog Thrust


Category	Accomplishment
Fundamental Analog (Circuits)	The Cascaded Time-Interleaved (CaTI) noise-shaping (NS) SAR ADC integrates high-order cascaded NS with bandwidth-enhanced time interleaving to surpass the bandwidth limitations of conventional NS SAR architectures. Fabricated in 28-nm CMOS, the prototype achieves 60-dB SNDR and 77.5-dB SFDR over 175 MHz without calibration, occupying 0.02 mm² and consuming 3.38 mW at 1.4 GS/s, corresponding to an FoM of 167 dB, demonstrating a robust and efficient alternative to traditional TI NS SAR ADCs. (3160.043, M. Flynn, University of Michigan)
Fundamental Analog (Circuits)	A multiphase (MP) subharmonic switching TX architecture improves both peak and power back-off efficiency while supporting wideband signals, featuring a phase-shifted subharmonic LO divider that suppresses subharmonic spurs, an MP LO generation scheme using a current-shared phase-interpolator, and a dual-rate hybrid DAC for noise shaping and reduced in-band EVM. A 65-nm CMOS prototype operating at 24 GHz achieves 22.3%/20.3% average PAE with −34.3 dB/−30.8 dB EVM at 1 Gb/s and 3.2 Gb/s data rates, respectively. (3160.008, M. Chen, University of Southern California)