Energy Efficiency

(Thrust leader: Ali Niknejad, UC Berkeley)

Figure 4. The research tasks include advanced SIMO DC-DC and hybrid LDO architectures with record fast transient response (Top left and middle, C. Huang, Iowa State University). Research is also focused on co-design of core voltage regulators, clocking, and automatically compiled designs (Top right, V. Sathe, Georgia Institute of Technology). Increasingly the focus of the research is at the intersection of power, energy, and AI/ML applications. Edge processing requires orders-of-magnitude reduction in inference AI power/energy consumption (Bottom left, M. Seok, Columbia University). Low power and energy efficiency is also demonstrated in novel PLL architectures for next generation high-speed links (Bottom middle, P. Hanumolu, University of Illinois Urbana-Champaigne). Ultra low power radios that break the trade-off between power consumption and sensitivity / performance employ novel phase noise cancellation architectures (Bottom right, D. Wentzloff, Michigan University).

The TxACE Energy and Efficiency (EE) thrust drives a comprehensive and interdisciplinary research agenda focused on advancing energy efficiency across the full spectrum of electronic systems—from sophisticated power management in data centers and end-user devices to the rapidly growing domains of low-power machine learning and AI at the edge. At its core, the EE thrust’s power management research serves as the cornerstone of the center, addressing fundamental challenges in improving efficiency for complex, large-scale systems. A key focus lies in digital multi-core platforms leveraging single-inductor multiple-output (SIMO) DC-DC converters, where efforts center on modeling, simulation, and performance optimization encompassing transient response and electromagnetic interference (EMI). These advances are achieved through the integration of nonlinear computational control, mixed-signal circuit techniques, adaptive algorithms, design automation, and machine-learning-assisted approaches. In addition, the thrust explores nontraditional hybrid power architectures and integration strategies for a broad range of applications—spanning high-performance computing, ultra-high conversion-ratio systems (from 48 V down to 1 V and below), and advanced battery charging solutions. Many of the proposed innovations harness mixed-signal methods that combine cutting-edge CMOS digital technology with GaN-based power devices, employing scalable analog architectures to enhance control precision, adaptability, and overall system flexibility, thereby paving the way for next-generation energy-efficient electronics.

Energy Efficiency Thrust


Category	Accomplishment
Energy Efficiency (Circuits)	An ultra-low-power, user-personalized on-device ASR system (tinyASR) whose accuracy rivals that of of large cloud-based models is demonstrated. TinyASR achieves speaker-specific performance through lightweight on-chip retraining of a 130-k parameter GRU model. The system fine tunes on only a few sentences per user with synthetic data generated via spectrogram augmentations. This approach with RNN architectures yields 94% phone-level accuracy, outperforming CNNs. Operating below 10 µW, tinyASR enables truly self-supervised, low-power personalization for edge devices, marking a major step toward ubiquitous intelligent IoT speech interfaces. (3160.002, M. Seok, Columbia University)
Energy Efficiency (Circuits)	An ultra-low-power receiver that achieves high data rates without sacrificing power efficiency is demonstrated. The receiver working with a co-optimized transmitter implements a phase-frequency error cancellation technique that mitigates phase noise, frequency drift, and carrier offset, thereby relaxing oscillator requirements and improving power efficiency. Fabricated in 65-nm CMOS, the 2.4-GHz transceiver employs 8-PSK double-sideband unsuppressed-carrier modulation and a Class-E PA. The RX achieves –74.5-dBm sensitivity at 1 Mbps and 419-µW DC power. The TX attains 38-% efficiency at 0-dBm output. (3160.015, D. Wentzloff, University of Michigan)
Energy Efficiency (Circuits)	Per-lane frequency multipliers and multi-phase clock generators for 100+ Gb/s serial links that eliminate the need for global clock distribution is demonstrated. A type-III wide-bandwidth ring-based sampling PLL with an NMOS-regulated voltage-controlled ring oscillator that extends the tuning range (6.8–14 GHz) and improves supply noise rejection by over 30 dB is demonstrated. A differential sampling phase detector cuts in-band noise, extends linearity by 4×, and suppresses even-order nonlinearities. The prototype achieved 67.5–69.3 fs RMS jitter and a 31 dB improvement in supply noise rejection. An integrated 0.4 ps-resolution digital-to-time converter provides 8-phase calibration with sub-0.05 ps accuracy through asynchronous sampling and continuous background tracking. (3160.017, P. Hanumolu, University of Illinois Urbana-Champaign)